In a typical procedure of bringing up a computer, a set of diagnostic programs is first run. The diagnostic programs are typically written to test specific components of the computer and, in the event of a failure, provide error message(s) identifying or isolating the cause(s) thereof. Upon completion of the diagnostic programs, benchmark application programs may also be executed. The benchmark application programs typically comprise routines that exercise the functions expected from the computer and are run to determine whether these functions are performed correctly thereby.
In running the test programs and/or the benchmark application programs, one often encounters failures that do not manifest themselves until after processing has proceeded for a substantial period of time past the failures, or failures (such as timing errors caused by unexpected capacitance in signal paths) that manifest only when the computer runs at full speed (as oppose to those that manifest in "single-cycle" which are relatively more easy to debug). When such types of failures occur, one vital debugging tool is to obtain a trace of the transactions performed by the computer. Tracing the transactions performed by the computer often means tracing the instructions it executes. From the trace, the activities of the computer during the time of a failure can be examined and from such activities the possible area of the failure can be isolated.
Tracing instructions is also useful for developing and debugging a computer software, where the trace can assist in understanding how and when problematic portions of the software are entered or exited.
Another often-used tool for debugging a computer system and/or computer software is to set breakpoints at selected addresses of the software. The breakpoints trap the flow of the software, such as whether, when and how certain portions of a software are entered and exited. From the flow, the behavior of the software can be examined.
Setting breakpoints also facilitates debugging and development of a computer or a computer software by allowing trial values to be injected at various processing stages of the software.
Tracing and trapping instructions are typically accomplished in prior art computers by a debug support circuit which is connected to the system bus--the bus that connects the CPU to the external memory and other peripheral devices. Connecting the debug support circuit to the system bus is convenient in prior art computers because it is where addresses, instructions and data of the computer flow. Moreover, by connecting the debug support circuit to the system bus, there is no need to add new input/output pins to a semiconductor chip; otherwise, the new I/O pins needed may be significant because instruction tracing requires outputting addresses whose length is normally equal to the width of the computer.
Unfortunately, providing the debug support circuit from the system bus also increases the electrical load of the system bus and interferes with the design and operation thereof. Moreover, debug support operations may be handicapped by shared use of the system bus, as they may be interfered by operations of the external memory and other peripheral devices.
Connecting the debug support circuit to the system bus is also undesirable for CPUs that use internal cache(s). In these CPUs, memory access is not performed if there is a cache hit; that is, instructions, data and addresses will not pass through the system bus when they are already present in the internal cache. If the instructions, data or addresses are accessed without passing through the system bus, they may become undetectable to the debug support device.
What is needed in view of the foregoing is a new debug support interface in a CPU whereby tracing and trapping of instructions can be achieved without using the system bus. Preferably, the new debug support interface allows tracing and trapping of instructions even when the CPU has an internal cache. Moreover, because increasing input/output pins of a semiconductor chip has an adverse effect on the cost and design thereof, it is also important that the new debug support interface does not significantly increase the number of input/output pins of the chip.